A quantitative approach – 6th American edition with a foreword by Norman P. Jouppi. Translation – Scientific Editing by Dimitris Gkizopoulos, University of Athens. The sixth edition of this classic textbook has been fully revised with the latest developments in processor and system architecture.

It now contains examples from the RISC-V instruction set architecture ("RISC Five"), a modern instruction set developed and designed to serve as an open and free adoptable standard. It also includes a new chapter on domain-specific architectures and an updated chapter on warehouse-scale computing, which presents the first publicly available information on Google's latest warehouse-scale computer.

Contents of the book: Introduction – Chapter 1: Basics of Quantitative Design and Analysis – Chapter 2: Designing the Memory Hierarchy – Chapter 3: Instruction Level Parallelism and its Exploitation – Chapter 4: Data Level Parallelism in Vector, SIMD, and GPU Architectures – Chapter 5: Thread Level Parallelism – Chapter 6: Warehouse Scale Computers for Exploiting Request Level and Data Level Parallelism – Chapter 7: Domain-Specific Architectures – Appendix A: Principles of Instruction Sets – Appendix B: Memory Hierarchy Overview – Appendix C: Pipelining: Basic and Intermediate Concepts – References – Index.

Key chapters of the book: It includes a new chapter on domain-specific architectures and explains how it is the only way to improve performance and energy efficiency given the end of Moore's Law and Dennard scaling. It presents four domain-specific architectures from the industry: Google's Tensor Processing Unit, Google's Pixel Visual Core, Intel's Nervana Neural Network Processor, and Microsoft's Catapult Accelerator.

It contains extensive updates in the chapter on warehouse-scale computing, including the first publicly available information on Google's latest warehouse-scale computer. It offers updates in other chapters, including new material related to the performance of NVIDIA's new Pascal GPU in comparison with Intel's new Skylake CPU with AVX-512 extensions, and extensive additions to the content covering the architecture and organization of multi-core processors.

They said about the book: "This sixth edition comes at a critical time: Moore's Law is fading just as deep learning systems demand unprecedented computational cycles. The new chapter on domain-specific architectures documents a number of promising approaches and predicts a renaissance in computer architecture. Like the scholars of the European Renaissance, computer architects will need to understand their own history, and then merge the lessons of that history with new techniques to reshape the world.” —Cliff Young, Google.

John L. Hennessy: Professor of Electrical Engineering and Computer Science, Emeritus President of Stanford University, ACM A.M. Turing Award, 2017. David A. Patterson: Distinguished Engineer, Google, Emeritus Professor of the Pardee Chair in Computer Science, University of California at Berkeley, ACM A.M Turing Award, 2017.